Senior Design Verification Engineer

About the role

Capgemini Engineering is expanding its Ukraine VLSI team and is looking for a Senior Design Verification Engineer. You will own verification of IPs and SoCs in prototype and design environments, establish functional and performance benchmarks, and lead the continuous improvement of verification methodologies.

Key responsibilities

• Own end‑to‑end verification of IP and SoC designs from RTL to emulation.
• Define, execute, and refine a robust design verification (DV) methodology across multiple platforms.
• Develop and maintain UVM/OVM test benches, UVC components, and sequences.
• Update verification environments for new feature bring‑up and architecture changes.
• Collaborate daily with Ukrainian engineers for knowledge sharing and technical guidance.

Required profile

• Strong knowledge of SystemVerilog and experience with constrained‑random and coverage‑driven verification using UVM or OVM.
• Hands‑on experience creating UVC components or sequences.
• Basic knowledge of at least two protocols (e.g., AHB/AXI, PCIe/CXL, USB, DDR, serial protocols) and deep expertise in one.
• Comfortable updating existing verification environments; building a UVM test bench from scratch is a plus.
• Proficiency in Perl, TCL, or Python scripting.
• Domain expertise in one area such as CPU/processor, multimedia, automotive, Ethernet, or mobile is preferred.

Required skills

• SystemVerilog
• UVM / OVM
• Constrained Random Verification
• Coverage Driven Verification
• UVC development
• AHB, AXI, PCIe, CXL, USB, DDR, Serial protocols
• Perl
• TCL
• Python

What we offer

• Competitive salary and benefits package.
• Access to experienced engineers for mentorship and knowledge sharing.
• Respect for work‑life balance and private life choices.
• All necessary tools for high‑performance verification work.
• Health insurance from day one, including during probation.
• Company holidays from December 25 to December 31.
• Support initiatives for veterans and psychological well‑being.